In “A Semidigital Dual Delay-Locked Loop” by S. Sidiropoulos and M. A. Horowitz, IEEE Journal of solid-state circuits, vol. 32, no. 11, November 1997 a dual delay-locked loop architecture is described which achieves low jitter, unlimited phase shift, and a large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation.
U.S. Pat. No. 5,134,637 discloses an improved clock recovery enchancement circuit that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of the bit rate clock, that is 180° out of phase with the recovering clock, thereby causing the data edges to appear to be locked. The clock recovery enhancement circuit, provides a window signal near a predefined edge of the recovering clock which creates a disable signal such that clock adjustments may be biased towards one direction. The generation of early/late information is therein defined as determining whether the detected data edge is early or late with respect to the corresponding edge of the recovered clock signal. If the detected data edge is early, then the recovered clock signal is accelerated by a recovery adjustment unit of time and, if the detected data edge is late, then the recovered clock signal is retarded by a like amount of time.